The present invention relates to digital signal processing technology which is applicable to the fields of sound, voice, communications, servo controls, etc. More particularly, it relates to techniques which are effective when applied to the multichannel arrangement of a hybrid analog/digital integrated circuit, such as a digital signal processor that has an analog circuit section including an A/D (analog-to-digital) conversion portion and a D/A (digital-to-analog) conversion portion, and a digital signal processing section for executing the multiply-and-sum computations etc. of digital signals.
In communications and other controls within the speech bandwidth as performed with a MODEM (modulator-demodulator), or ISDN (integrated speech/data network), etc., it is possible to employ a digital signal processor which has an A/D converter as well as a D/A converter and a digital signal processing section. Heretofore, various techniques have been proposed in order to enhance the versatility and applicability of the digital signal processor.
For example, a digital signal processor having an analog circuit section in which the functions of a D/A converter and a sequential comparison type A/D converter configured of a comparator circuit and an D/A converter circuit may be selected in time division as stated in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, No. 1, Feb. 1980, pp. 33-38. The digital signal processor is operated as follows: One of a plurality of analog signal input pins is selected to apply a corresponding analog signal to the analog circuit section through a multiplexer formed on the same chip as that of the analog circuit section. An output from the analog circuit section is delivered to a selected one of a plurality of analog signal output pins through a demultiplexer formed on the same chip. Thus, the digital signal processor achieves the multichannel processing of analog inputs to and from the analog circuit section in which the A/D conversion function and D/A conversion function are selected in time division.
In addition, a digital signal processor disclosed in the official gazette of Japanese Patent Application Laid-open No. 217706/1988 is intended to enhance the versatility and is adapted to programmably set the signal frequency bands of a prefilter arranged at the input stage of an A/D converter and of a postfilter arranged at the output stage of a D/A converter. Each of the respective filters serve to eliminate folded noise.
Also, the official gazette Japanese Utility Model Registration Application Laid-open No. 1423 /1987 discloses a digital signal processor in which the conversion cycle of one set of A/D and D/A converters is changed at will, thereby rendering the applicable processing multifarious.